Opening Multi-Project Wafer programmes to European fabless SMEs
VOICES position paper to the Chips Joint Undertaking with six concrete recommendations on MPW design windows, SME-tiered pricing, and open PDK policy.
The policies being written today will determine whether European fabless companies thrive or fade. EFSA makes sure the right voices are in the room.
Europe's €43 billion Chips Act is the most ambitious semiconductor investment programme in the continent's history. But ambition without structure risks becoming subsidy. Without dedicated representation, fabless SMEs will remain invisible in the rooms where those funds are allocated — and the benefits will flow, as they have before, to large manufacturers and foreign acquirers.
EFSA's policy mission is simple: make sure that the fabless model is understood, respected, and actively supported at every level of European semiconductor governance.
We engage directly with DG CONNECT (digital and semiconductor policy), DG GROW (industrial policy and SME support), and DG RTD (research and innovation funding), ensuring that fabless perspectives inform the priorities, eligibility criteria, and support mechanisms of EU programmes.
The Chips JU governs Europe's most important semiconductor infrastructure investments — pilot lines, competence centres, and the shared design platform. EFSA advocates for SME-accessible design windows, flexible MPW programmes, and open PDK policies that allow fabless startups to use these facilities.
We engage with MEPs on the Industry, Research and Energy Committee (ITRE) and the Digital Committee to provide technical input on semiconductor legislation, digital sovereignty initiatives, and deep-tech investment frameworks.
EFSA works with ministries of industry, innovation, and digital affairs across EU member states — ensuring that national fabless ecosystems are represented and that local companies can access both national and European opportunities.
Design-access provisions in the Chips Act — ensuring fabless SMEs can access pilot lines, MPW programmes, and the EU Design Platform without prohibitive costs or bureaucratic barriers.
Scale-up finance — advocating for patient capital instruments, hybrid debt-equity vehicles, and EU co-investment programmes calibrated to the 7-15 year development cycles of semiconductor hardware.
IP and open-source — supporting open PDK initiatives and pre-competitive IP sharing frameworks that reduce barriers to entry for startups.
Talent and education — ensuring semiconductor curricula, post-doctoral programmes, and apprenticeship schemes produce the chip designers Europe needs.
Procurement and market access — working to increase European procurement of European-designed chips across defence, space, automotive, and public sector applications.
Fabless-specific infrastructure — advocating for EDA tool access programmes, shared verification environments, and foundry-access agreements that level the playing field with US and Asian competitors.
VOICES position paper to the Chips Joint Undertaking with six concrete recommendations on MPW design windows, SME-tiered pricing, and open PDK policy.
Twelve detailed recommendations covering onboarding, tooling, IP frameworks, and SME governance representation for the EU Design Platform.
Quantitative analysis of the deep-tech funding gap as it affects fabless semiconductor companies in the EU, with policy recommendations.